I have a new ISA for this one which I'm calling Bones. 32 op(codes), 16-bit word, 16-bit memory byte, MISC, 5 general-purpose regs and a stack, reg+offset indirect addressing, and more, all designed to be relatively easy to make out of 74-series logic chips.
There is a user mode and kernel mode.
There are no immediates, you use an instruction to set the high byte of the next instruction's literal if you need numbers further from 0 than -128 through 127.
Some main project goals:
* Not too many 74-series chips required to create. [Terribly rough estimate: under 150 chips]
* The ISA and physical architecture elegantly line up.
* The ISA doesn't highly prioritize ISA future-proofing.
* Not a drag to asm program in!
* About as powerful as a 16-bit machine might be expected to be. Practical (not like Ben Eater's CPU), but more barebones than Bill Buzbee's CPU.
* No microcode -- pure bare-metal.
Inspired by Buzbee I decided to design-in virtual memory into my system as well; my current design has 128KiB virtual address space (per process), 4KiB pages, and up to 256MiB of physical memory. Unlike Buzbee's computer, mine unfortunately doesn't support page faults; the virtual memory system is solely for memory protection, allowing fast memory reallocation (e.g. no memory compaction), and allowing more than 128K of physical RAM.